A semiconductor wafer used in the present-day production of a semiconductor device is made of silicon produced by, for example, Czochralski method (CZ method). In the device process, the temperature has become lower and the integration has become higher, it has been revealed that low-density Grown-in defects have an effect on a characteristic of the device.
Such a Grown-in defect has a shape of an independent or multiply connected structure based on an octahedral void when the defect exists inside crystal, and becomes a concave-shaped pit of a quadrangular pyramid when the defect is exposed to surface after the crystal is processed in a wafer state. And, after the crystal is sliced into a wafer, COP that is a defect pit appearing by performing mirror-polishing and wafer-cleaning has had an effect on oxide dielectric breakdown voltage.
Conventionally, according to slow cooling in the growth by CZ method, the Grown-in defect that is an octahedral void has been planned to be reduced. However, on the other hand, its size has comes to increase. As the device pattern has become even finer, it has become impossible to ignore a size of the Grown-in defect with comparing the Grown-in defect size to a size of the pattern. And, a wafer that has almost none of the Grown-in defects in a device region has been required.
Accordingly, in a frontier process of 64MDRAM, an epitaxial wafer having no Grown-in defects or a hydrogen-argon annealed wafer having a disappearance effect of the Grown-in defects in the vicinity of a surface has been mass-produced and used (see, for example, Japanese Patent Application (Kokai) No. 51-134071 and No. 60-247935).
However, in the case of producing the annealed wafer, it is known that if a silicon wafer is heat-treated under an atmosphere of an argon gas at a high temperature, resistivity of the silicon wafer is changed (for example, Realize Co., Ltd., “Chemical Contamination in an Semiconductor Process Environment and Measures for it (1997), page 60”). It has been estimated that this is because phosphorous or boron from the environment, the heat treatment furnace, and so forth, adheres to the silicon wafer and, diffuses into the inside of the wafer by performing the high-temperature heat treatment in the state, and consequently the resistivity is changed.
As the measures for this, for example, in Japanese Patent Application (Kokai) No. 2002-100634, it is proposed that in order to prevent boron contamination from the environment, a hydrogen gas is contained in the atmosphere in a temperature region of 950-1100° C. in the heat treatment. This is for removing the boron by utilizing out-diffusion of boron by a high-temperature heat treatment in a hydrogen gas atmosphere, so that the resistivity in a surface layer of the wafer is prevented from changing.
Moreover, in Japanese Patent Application (Kokai) No. 2004-207601, there has been presented a method that the silicon wafer is preliminarily heated at a low temperature before the high-temperature heat treatment, and therefore the phosphorous adhering to the silicon wafer from the environment and the heat treatment furnace and so forth are removed, and thereby resistivity in the vicinity of the surface layer of the wafer is prevented from changing due to phosphorous contamination.
However, even when these methods are used for producing an annealed wafer, the wafer has been contaminated with conductive impurities such as phosphorous in the heat treatment, and resistivity of the wafer cannot be certainly prevented from changing before and after the heat treatment.